Miniaturization of semiconductor circuits is generally achieved by either decreasing the size of the semiconductor chip assigned to each memory cell and/or increasing the size of the chip. Because a substantial loss and yield occurs as the chip area increases, miniaturization of semiconductor circuits using this process has typically been too complex and uneconomical to pursue. Therefore, substantial efforts have been made in the integrated circuit industry to reduce the size of the individual circuit components within a given area.
For example, U.S. Pat. No. 4,796,074 discloses a method of fabricating a high density mass programmable read-only memory. The read-only memory is comprised of a plurality of memory cells. Each cell comprises a Schottky diode which is configured vertically with an antifuse structure. The inclusion of a Schottky diode, which is prevalent in many prior art structures, increases the total cell size. Moreover, it has been noted that a Schottky diode as part of the antifuse vertical structure has an inherent reliability problem because of the resulting barrier between the metallization layer and the lightly doped semiconductor layer. See, for example, U.S. Pat. No. 4,569,121, issued to Lim et al., col. 6, 43-63.
Therefore, a need arises for a method of manufacturing a programmable semiconductor antifuse structure without an associated structure, such as a Schottky diode, and having an area of less than one micron.